From: Advaith Menon Date: Fri, 6 Feb 2026 15:32:49 +0000 (-0500) Subject: Finish onboarding X-Git-Url: https://git.devinivas.org/?a=commitdiff_plain;h=81aaca7dcb594d6175889404ebd857f3d9fb9717;p=sij-ddsp26.git Finish onboarding *Interchange memory outputs --- diff --git a/sim/behav/mismatches.txt b/sim/behav/mismatches.txt deleted file mode 100644 index 5452dbb..0000000 --- a/sim/behav/mismatches.txt +++ /dev/null @@ -1,518 +0,0 @@ -Comparison Results -Expected file: /nethome/amenon301/Documents/siliconj_NEW/Spring26-DD-Onboarding-main/sim/behav/WORKSPACE/memory_post_state_upper.txt -Simulation file: /nethome/amenon301/Documents/siliconj_NEW/Spring26-DD-Onboarding-main/sim/behav/WORKSPACE/sim_memory_post_state_upper.txt -Total mismatches: 128 -====================================================================== - -Mismatch at line 385: - Expected: '11011011000010110111001001011111' - Sim output: '01011100000100001001100010110011' - -Mismatch at line 386: - Expected: '11010100011110010101001101101001' - Sim output: '11001101000111110110001110110001' - -Mismatch at line 387: - Expected: '01010111101101110101101011101001' - Sim output: '01101001111100100010110100000110' - -Mismatch at line 388: - Expected: '01010000100100111111110100011010' - Sim output: '11110011011111100010101011011101' - -Mismatch at line 389: - Expected: '00010010010111110100001101100111' - Sim output: '01010001000010001101011010111001' - -Mismatch at line 390: - Expected: '11110100101010101011000010101000' - Sim output: '00000111001011001010000101011100' - -Mismatch at line 391: - Expected: '10011011000010010100000001000100' - Sim output: '11011100111111000000001000011011' - -Mismatch at line 392: - Expected: '00110110011100110100000011011010' - Sim output: '00001110111010101001010011101000' - -Mismatch at line 393: - Expected: '00011011100100111010011001010111' - Sim output: '11011110001000000111001100100001' - -Mismatch at line 394: - Expected: '00110100100110101010100111001100' - Sim output: '01000100011011100000011111010100' - -Mismatch at line 395: - Expected: '11101101100111001101111001000100' - Sim output: '00101010001110101100001111111101' - -Mismatch at line 396: - Expected: '01010110000011000111100011011000' - Sim output: '00111011000111001011011100010110' - -Mismatch at line 397: - Expected: '00011111010101000000000100010110' - Sim output: '01001100010100010000011111110010' - -Mismatch at line 398: - Expected: '10110010010111101000001001101000' - Sim output: '10110001100101101110001111001010' - -Mismatch at line 399: - Expected: '01111000111111000011000011101100' - Sim output: '10000100010011111000101001011100' - -Mismatch at line 400: - Expected: '00111000000000100010011010000101' - Sim output: '01101111010010001011000001001000' - -Mismatch at line 401: - Expected: '00011111011011101110110110111100' - Sim output: '00111100111000100111010110100010' - -Mismatch at line 402: - Expected: '01111001101000111010101011011000' - Sim output: '00010001000110111101010011111001' - -Mismatch at line 403: - Expected: '11110111101111011101001010000110' - Sim output: '01101011001101110010111000011001' - -Mismatch at line 404: - Expected: '01000001000101100101111010101000' - Sim output: '11111010111100001110100101001110' - -Mismatch at line 405: - Expected: '10010010000011111110010010001010' - Sim output: '01100000101001101101110010111010' - -Mismatch at line 406: - Expected: '10111111100010100001000001001010' - Sim output: '10001110111100000011100110111101' - -Mismatch at line 407: - Expected: '00111011110010101010000000011100' - Sim output: '01100001101110101011100110111101' - -Mismatch at line 408: - Expected: '10101101101110000100101101011111' - Sim output: '00010001011110000001101101110100' - -Mismatch at line 409: - Expected: '11001010100000101001101011000101' - Sim output: '01111100010110101111011111110110' - -Mismatch at line 410: - Expected: '10001010011101101001110101001110' - Sim output: '11100010011010111110011100100001' - -Mismatch at line 411: - Expected: '10010111010000000011101001110011' - Sim output: '11011011100111010010111001011101' - -Mismatch at line 412: - Expected: '01011010101101000100011101110100' - Sim output: '01000100110110000101101111010010' - -Mismatch at line 413: - Expected: '10010001010000011110110100110110' - Sim output: '00001011010111101111111010110111' - -Mismatch at line 414: - Expected: '11000001100100000101111010111011' - Sim output: '10100110101110110100000001110110' - -Mismatch at line 415: - Expected: '00110101111000010000110000001010' - Sim output: '11010010000001111011001001111000' - -Mismatch at line 416: - Expected: '11101001001111000011100100000101' - Sim output: '11101110110010111110010001010111' - -Mismatch at line 417: - Expected: '01110001011000001101100100000110' - Sim output: '00100110101100001011110110010000' - -Mismatch at line 418: - Expected: '01000000001101010000010111001110' - Sim output: '11010111011001100100001111111110' - -Mismatch at line 419: - Expected: '10011111011111001001111100010110' - Sim output: '11100001110001101100111100101111' - -Mismatch at line 420: - Expected: '10000110101111011111111011000011' - Sim output: '11101110010111101111011001100110' - -Mismatch at line 421: - Expected: '01011100010100101000001001001011' - Sim output: '01100101010010100000110110010001' - -Mismatch at line 422: - Expected: '00011111000000110010011010100001' - Sim output: '11101001011010011110011110101011' - -Mismatch at line 423: - Expected: '10101001000010001011001110101001' - Sim output: '11010111100000010011101100101000' - -Mismatch at line 424: - Expected: '01011000101100101011011010110100' - Sim output: '10010000001010110011001101110100' - -Mismatch at line 425: - Expected: '01010101000011000011111010101101' - Sim output: '11010110100100000011010011101110' - -Mismatch at line 426: - Expected: '01111000000010000111001011010100' - Sim output: '11100111000011111110101110011010' - -Mismatch at line 427: - Expected: '10101011010001000001010000011110' - Sim output: '11000001111101001101100000110110' - -Mismatch at line 428: - Expected: '10000101100000001111011111000010' - Sim output: '11010011000101010001100111110110' - -Mismatch at line 429: - Expected: '11001110100101110010101001110110' - Sim output: '00011111110010011110111110101010' - -Mismatch at line 430: - Expected: '00111101111001000100011100101000' - Sim output: '00101001010101110101011100000100' - -Mismatch at line 431: - Expected: '11010101010100101010000000001111' - Sim output: '10100111011101110111111100001011' - -Mismatch at line 432: - Expected: '00110101100110011010010101001100' - Sim output: '10010110110011111101110111001100' - -Mismatch at line 433: - Expected: '01001001111000100001001011100000' - Sim output: '00001110111000111000100100001000' - -Mismatch at line 434: - Expected: '01000010100011110111001101110001' - Sim output: '00111001111111010010001111111111' - -Mismatch at line 435: - Expected: '11011100001000101110000001100011' - Sim output: '10001001000001000000101000010100' - -Mismatch at line 436: - Expected: '01100001110000010001111011111000' - Sim output: '00011111011011010110011001010111' - -Mismatch at line 437: - Expected: '00111001001000111011011110001010' - Sim output: '10101011111010100001000000110110' - -Mismatch at line 438: - Expected: '01101110110011000000011010010001' - Sim output: '01001100011000100010011100111001' - -Mismatch at line 439: - Expected: '00001100100000011111010111111101' - Sim output: '00001000110111010000001100010101' - -Mismatch at line 440: - Expected: '01011110010110000111101100101000' - Sim output: '00001110001100010100101001101110' - -Mismatch at line 441: - Expected: '00100100011111110000000001011111' - Sim output: '00111011010010111011000100011001' - -Mismatch at line 442: - Expected: '01001001001000101001011111010000' - Sim output: '11101001111000000011001001011011' - -Mismatch at line 443: - Expected: '01001001110001011100111101101011' - Sim output: '00110110110101111011110001100100' - -Mismatch at line 444: - Expected: '10011100110001110100100111000001' - Sim output: '00111101001110000111111110000010' - -Mismatch at line 445: - Expected: '01011000010101111000011111011100' - Sim output: '00010101011100000100100000010010' - -Mismatch at line 446: - Expected: '10110000111101100110101011111110' - Sim output: '10011011100101111110101000001111' - -Mismatch at line 447: - Expected: '00111001001011101011110101110100' - Sim output: '01000010101111100111011111001001' - -Mismatch at line 448: - Expected: '11010101000010110110011010000101' - Sim output: '10111100010010100010000000001000' - -Mismatch at line 449: - Expected: '00001100111001011011001110000010' - Sim output: '01011100100011000111010111101111' - -Mismatch at line 450: - Expected: '01101001001010110110000001101001' - Sim output: '00111001011100010101100111100011' - -Mismatch at line 451: - Expected: '00001010010010011101111111100001' - Sim output: '01110000111010001111110100110101' - -Mismatch at line 452: - Expected: '01011100101110110010111100000111' - Sim output: '11000011110111011100000001100001' - -Mismatch at line 453: - Expected: '11100110011001000010000001001100' - Sim output: '11110001011100110011100101101001' - -Mismatch at line 454: - Expected: '10100111101001010111101000011101' - Sim output: '01011101110101001101110100001101' - -Mismatch at line 455: - Expected: '11111101000011100000001001110111' - Sim output: '01010100011000001101000100000100' - -Mismatch at line 456: - Expected: '01111011101110000011011111100100' - Sim output: '11000000100100001111011100011100' - -Mismatch at line 457: - Expected: '01000111111001110111110001110010' - Sim output: '00110001010001110100011101101000' - -Mismatch at line 458: - Expected: '01100100010001001110111100111110' - Sim output: '11000110011101001101000101001010' - -Mismatch at line 459: - Expected: '01001010011000011111110001110110' - Sim output: '11101011001000100010111100101001' - -Mismatch at line 460: - Expected: '00011011011100111100110100000111' - Sim output: '11111000010110011000100000010101' - -Mismatch at line 461: - Expected: '01111000100000011011111110001011' - Sim output: '11000100001101110101001001110100' - -Mismatch at line 462: - Expected: '10110011111010100111100000000110' - Sim output: '00011100001100000000001010001000' - -Mismatch at line 463: - Expected: '00111001110101010110111011101010' - Sim output: '10101101101100101111000110010010' - -Mismatch at line 464: - Expected: '10111001011000111101110110011101' - Sim output: '10100101110010111001111100001101' - -Mismatch at line 465: - Expected: '11010101110101110000110111010010' - Sim output: '11111001001001000000111010010100' - -Mismatch at line 466: - Expected: '01010011000101001010110100010010' - Sim output: '00010010110111011111001011001100' - -Mismatch at line 467: - Expected: '10001010101000000010000100101010' - Sim output: '00000011010001111010000010101010' - -Mismatch at line 468: - Expected: '00001101000000110001100000001001' - Sim output: '10101011011111001101110000111110' - -Mismatch at line 469: - Expected: '00001010100000111100100000100111' - Sim output: '11110011110001100110000010011100' - -Mismatch at line 470: - Expected: '01101000010100111010111001010000' - Sim output: '00001101011100101100110000010001' - -Mismatch at line 471: - Expected: '10001011011100010100010111101110' - Sim output: '01001001001100011110110010111111' - -Mismatch at line 472: - Expected: '10000010011110000000101001100011' - Sim output: '10011010100011101111101001101101' - -Mismatch at line 473: - Expected: '00111111001000001111100011001110' - Sim output: '11100000100000000101000010100101' - -Mismatch at line 474: - Expected: '01101110101100011111101100011011' - Sim output: '10010110011111010011110000111100' - -Mismatch at line 475: - Expected: '01000111101110101111111011011001' - Sim output: '10010001001101111010010100010011' - -Mismatch at line 476: - Expected: '00001011111001111000100000000100' - Sim output: '01010010001001110001010001111100' - -Mismatch at line 477: - Expected: '01000101111001100011100101010001' - Sim output: '11010011110000110111101011111010' - -Mismatch at line 478: - Expected: '00011100101001000000100010011111' - Sim output: '01001100100111110001000011101001' - -Mismatch at line 479: - Expected: '00100011010000000010110001001011' - Sim output: '00010110001111001111001010011100' - -Mismatch at line 480: - Expected: '11111010100101111011110101010111' - Sim output: '10111111000010111000001000111011' - -Mismatch at line 481: - Expected: '00010000011110100010011001000111' - Sim output: '11101111011011010100010011101111' - -Mismatch at line 482: - Expected: '01010101111011000010000101100010' - Sim output: '01001100011000000001110011111011' - -Mismatch at line 483: - Expected: '01011101100010001111110001100110' - Sim output: '01000010011010100111000000101111' - -Mismatch at line 484: - Expected: '01000010101111111100100111010100' - Sim output: '00110011110010100010011100101100' - -Mismatch at line 485: - Expected: '00011010011110011011010000010001' - Sim output: '01011001110100011101101000100001' - -Mismatch at line 486: - Expected: '10011110010010010111100001000110' - Sim output: '11010011100101111100011011011010' - -Mismatch at line 487: - Expected: '00000010111000001111101001001110' - Sim output: '11010000010011011011100010011001' - -Mismatch at line 488: - Expected: '01010011110011100001100101000111' - Sim output: '00011111011010000110001010111101' - -Mismatch at line 489: - Expected: '00110011111111001100000101111111' - Sim output: '11101001001001111011010101000111' - -Mismatch at line 490: - Expected: '10001110100011110101100110011111' - Sim output: '10001010000101111011011001100111' - -Mismatch at line 491: - Expected: '11000110100010010011010111001011' - Sim output: '00010100000111110011110111000001' - -Mismatch at line 492: - Expected: '10100010011111011001100010011000' - Sim output: '01111001001100100000000110111001' - -Mismatch at line 493: - Expected: '11110110110010011000111110110010' - Sim output: '00010101011000001100010001111111' - -Mismatch at line 494: - Expected: '01000100011000010101110011010000' - Sim output: '11101000110100101100011000111100' - -Mismatch at line 495: - Expected: '00100111011001101111001100100110' - Sim output: '11000011011111011011001101100001' - -Mismatch at line 496: - Expected: '01111101011011110010111110011000' - Sim output: '01101110011111010011111111011100' - -Mismatch at line 497: - Expected: '10000000011001100100000011101001' - Sim output: '00010101001011100101001100001011' - -Mismatch at line 498: - Expected: '00111111001010110111111101111011' - Sim output: '10011000011001000110100110011100' - -Mismatch at line 499: - Expected: '01110001100101000110111011100001' - Sim output: '11101011110000110111000110111011' - -Mismatch at line 500: - Expected: '11101101001111000011111010011111' - Sim output: '10000110101001000101101010001110' - -Mismatch at line 501: - Expected: '11110000001101011101111101000110' - Sim output: '11100111000110010101101111011101' - -Mismatch at line 502: - Expected: '00000110000101001110000000010110' - Sim output: '11101111101111101010110010101011' - -Mismatch at line 503: - Expected: '00011001000111010001011011001100' - Sim output: '01101111100111111111100101111110' - -Mismatch at line 504: - Expected: '00110011100001001101110000100001' - Sim output: '01100001001100111000010111110010' - -Mismatch at line 505: - Expected: '11111001100001011110110001001111' - Sim output: '10100111101000000010111001111110' - -Mismatch at line 506: - Expected: '01110010011100001000001000011011' - Sim output: '11111000011100100010100111110010' - -Mismatch at line 507: - Expected: '11110000001100011100001011111000' - Sim output: '11011001001111100101110000000111' - -Mismatch at line 508: - Expected: '01110100110101100000011100001011' - Sim output: '01000111111100010110110111000101' - -Mismatch at line 509: - Expected: '01101001110110010101100110000000' - Sim output: '10101000101011110000110101010100' - -Mismatch at line 510: - Expected: '11110110110110110000111000000010' - Sim output: '11101010000101000100100011111011' - -Mismatch at line 511: - Expected: '01011000100010010000001101110100' - Sim output: '01111100011110001100011000111010' - -Mismatch at line 512: - Expected: '11100111111010110001111110101111' - Sim output: '00111111011100010011001000000110' - diff --git a/src/verilog/calculator_pkg.sv b/src/verilog/calculator_pkg.sv index 1abd131..2f1691c 100644 --- a/src/verilog/calculator_pkg.sv +++ b/src/verilog/calculator_pkg.sv @@ -16,7 +16,7 @@ package calculator_pkg; // TODO: Declare additional state(s) as needed // DO NOT REMOVE S_IDLE AND S_END STATES - typedef enum logic [2:0] {S_IDLE,S_READ,S_RD2,S_ADD,S_WRITE,S_WT2,S_END} state_t; + typedef enum logic [3:0] {S_IDLE,S_READ,S_RD_DUMMY1,S_RD2,S_RD_DUMMY2,S_ADD,S_WRITE,S_WT2,S_END} state_t; typedef enum logic {LOWER, UPPER} buffer_loc_t; endpackage diff --git a/src/verilog/controller.sv b/src/verilog/controller.sv index 50da3a2..724788a 100644 --- a/src/verilog/controller.sv +++ b/src/verilog/controller.sv @@ -53,7 +53,7 @@ module controller import calculator_pkg::*;( //========================================================================= // Declare state machine states - typedef enum logic [2:0] {S_IDLE,S_READ,S_RD2,S_ADD,S_WRITE,S_WT2,S_END} state_t; + typedef enum logic [3:0] {S_IDLE,S_READ,S_RD_DUMMY1,S_RD2,S_RD_DUMMY2,S_ADD,S_WRITE,S_WT2,S_END} state_t; typedef enum logic {LOWER, UPPER} buffer_loc_t; state_t state, next; // buffer_loc_t buffer_loc; @@ -62,6 +62,8 @@ module controller import calculator_pkg::*;( logic [ADDR_W-1:0] curr_addr_ff; logic [ADDR_W-1:0] curr_waddr_s; logic [ADDR_W-1:0] curr_waddr_ff; + logic [MEM_WORD_SIZE-1:0] curr_r_data_s; + logic [MEM_WORD_SIZE-1:0] curr_r_data_ff; logic curr_half_s; logic curr_half_ff; @@ -84,12 +86,14 @@ module controller import calculator_pkg::*;( curr_waddr_ff <= 8'h0; curr_half_ff <= 1'b0; addr_ci_ff <= 1'b0; + curr_r_data_ff <= 32'bx; end else begin state <= next; curr_addr_ff <= curr_addr_s; curr_waddr_ff <= curr_waddr_s; curr_half_ff <= curr_half_s; addr_ci_ff <= addr_ci_s; + curr_r_data_ff <= curr_r_data_s; end end @@ -101,12 +105,13 @@ always_comb begin r_addr = curr_addr_ff; w_addr = curr_waddr_ff; w_data = 'b0; - carry_in = addr_ci_ff; + //carry_in = addr_ci_ff; curr_addr_s = curr_addr_ff; curr_waddr_s = curr_waddr_ff; curr_half_s = curr_half_ff; addr_ci_s = addr_ci_ff; + curr_r_data_s = curr_r_data_ff; case (state) S_IDLE: begin @@ -125,28 +130,58 @@ always_comb begin /* read memory */ read = 1'b1; write = 1'b0; - r_addr = curr_addr_ff; + //r_addr = curr_addr_ff; /* move next */ //next = S_RD2; // timing - next = S_ADD; - curr_half_s = curr_half_ff; + next = S_RD_DUMMY1; + /* save carry over from previous comp.: only for upper word */ + //addr_ci_s = carry_out; + end + S_RD_DUMMY1: begin + read = 1'b1; + write = 1'b0; + next = S_RD2; + curr_r_data_s = r_data; + /* read the next address */ + curr_addr_s = curr_addr_ff + 1; end S_RD2: begin //ign + read = 1'b1; + write = 1'b0; + r_addr = curr_addr_ff; + /* move next */ + //next = S_RD2; // timing + next = S_RD_DUMMY2; + end + S_RD_DUMMY2: begin + read = 1'b1; + write = 1'b0; next = S_ADD; end S_ADD: begin - /* a = our address from memory bank (64 bit word) */ - op_a = r_data[MEM_WORD_SIZE-1:DATA_W]; /* high word */ - op_b = r_data[DATA_W-1:0]; /* low word */ if (curr_half_ff) begin next = S_WRITE; + /* a = our address from memory bank (64 bit word) */ + op_a = curr_r_data_s[MEM_WORD_SIZE-1:DATA_W]; /* high word */ + op_b = r_data[MEM_WORD_SIZE-1:DATA_W]; /* hi word */ + /* carry in from previous */ + carry_in = addr_ci_ff; + addr_ci_s = 1'b0; + /* move to the next word */ + curr_addr_s = curr_addr_ff + 1; end else begin + next = S_READ; + /* move to the next address for our nice folks here :) */ + curr_addr_s = curr_addr_ff + 1; + op_a = curr_r_data_s[DATA_W-1:0]; /* low word 1 */ + op_b = r_data[DATA_W-1:0]; /* low word 2 */ + carry_in = 0; /* set carry in to carry out for the next state */ /* we have to add once more */ addr_ci_s = carry_out; - next = S_READ; + /* move to the start to fetch higher addresses */ + curr_addr_s = curr_addr_ff - 1; end - curr_addr_s = curr_addr_ff + 1; curr_half_s = !curr_half_ff; end S_WRITE: begin diff --git a/src/verilog/top_lvl.sv b/src/verilog/top_lvl.sv index e4f39f5..61ac6c6 100644 --- a/src/verilog/top_lvl.sv +++ b/src/verilog/top_lvl.sv @@ -127,11 +127,11 @@ module top_lvl import calculator_pkg::*; ( ); // FIXME Advaith new RAM CF_SRAM_1024x32_macro sram_A ( - .DO (sram1_dout_s), // data output + .DO (sram2_dout_s), // data output .DI (sram1_din_s), // data input .AD (sram1_addr_s), // 10-bit address .CLKin (clk), // Clock input - .EN (sram1_cs_s || ~sram1_we_s), // Global enable + .EN (~(sram1_cs_s && sram1_we_s)), // Global enable .R_WB (sram1_we_s), // Read enable // DO NOT MODIFY THE FOLLOWING PINS @@ -150,11 +150,11 @@ module top_lvl import calculator_pkg::*; ( // TODO check enable signals CF_SRAM_1024x32_macro sram_B ( - .DO (sram2_dout_s), // data output + .DO (sram1_dout_s), // data output .DI (sram2_din_s), // data input .AD (sram2_addr_s), // 10-bit address .CLKin (clk), // Clock input - .EN (sram2_cs_s || ~sram2_we_s), // Global enable + .EN (~(sram2_cs_s && sram2_we_s)), // Global enable .R_WB (sram2_we_s), // Read enable // DO NOT MODIFY THE FOLLOWING PINS