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Initial commit
authorAdvaith Menon <amenon301@gatech.edu>
Thu, 5 Feb 2026 02:02:10 +0000 (21:02 -0500)
committerAdvaith Menon <amenon301@gatech.edu>
Thu, 5 Feb 2026 02:02:10 +0000 (21:02 -0500)
commit891fff289a88891b90c5ec7755dd69ebb579ffea
treecb61697be529cc8d5665723b443d0f8bf28cdbcatree | snapshot
Initial commit
* Based on Fall 2025
37 files changed:
.gitignore [new file with mode: 0644] blob
README.md [new file with mode: 0644] blob
resources/calculator.drawio.png [new file with mode: 0644] blob
resources/cycle_count.png [new file with mode: 0644] blob
resources/hdlbit-roadmap.md [new file with mode: 0644] blob
resources/sram_addressing.drawio.png [new file with mode: 0644] blob
resources/suggested_fsm.drawio.png [new file with mode: 0644] blob
resources/timing_diagram.jpg [new file with mode: 0644] blob
screenshots/Add_to_wave_view.png [new file with mode: 0644] blob
screenshots/Change_radix.png [new file with mode: 0644] blob
screenshots/Initial_View.png [new file with mode: 0644] blob
screenshots/cycle_count.png [new file with mode: 0644] blob
screenshots/example_submission.png [new file with mode: 0644] blob
screenshots/fastxSetup1.png [new file with mode: 0644] blob
screenshots/fastxSetup2.png [new file with mode: 0644] blob
screenshots/fastxSetup3.png [new file with mode: 0644] blob
screenshots/simvision.png [new file with mode: 0644] blob
scripts/check_onboarding.py [new file with mode: 0644] blob
scripts/init_mem.py [new file with mode: 0644] blob
sim/behav/Include/calculator.include [new file with mode: 0644] blob
sim/behav/Makefile [new symlink] blob
sim/behav/link_files.py [new file with mode: 0644] blob
sim/behav/mismatches.txt [new file with mode: 0644] blob
sim/behav/simvision.svcf [new file with mode: 0644] blob
src/Makefiles/Makefile [new file with mode: 0644] blob
src/python_model/memory_post_state [new file with mode: 0644] blob
src/python_model/memory_pre_state [new file with mode: 0644] blob
src/python_model/new_dd_onboarding.ipynb [new file with mode: 0644] blob
src/verilog/.adder32.sv.swn [new file with mode: 0644] blob
src/verilog/CF_SRAM_1024x32.tt_180V_25C.v [new file with mode: 0644] blob
src/verilog/adder32.sv [new file with mode: 0644] blob
src/verilog/calculator_pkg.sv [new file with mode: 0644] blob
src/verilog/controller.sv [new file with mode: 0644] blob
src/verilog/full_adder.sv [new file with mode: 0644] blob
src/verilog/result_buffer.sv [new file with mode: 0644] blob
src/verilog/tb_calculator.sv [new file with mode: 0644] blob
src/verilog/top_lvl.sv [new file with mode: 0644] blob
SiliconJackets Digital Design Onboarding Sp26